IP-NCO【PDF 19/54 页】IP NCO COMPILER

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Chapter 2: Getting Started

2–7

MegaWizard Plug-In Manager Flow

Table 2–1 describes the generated files and other files that may be in your project

directory. The names and types of files specified in the report vary based on

whether you created your design with VHDL or Verilog HDL.

Table 2–1. IP Toolbench Files

Filename (1) , (2)

< entity name >.v

< variation name >_vho_msim.tcl

< variation name >_vo_msim.tcl

< variation name >_tb.v or

< variation name >_tb.vhd

< variation name > .bsf

< variation name > .cmp

< variation name > .html

< variation name >.qip

< variation name >.vec

< variation name >.vhd or .v

< variation name >.vho or

< variation name >.vo

< variation name >_bb.v

< variation name > _cos_c.hex,

< variation name > _cos_f.hex,

< variation name > _sin_c.hex,

< variation name > _sin_f.hex

< variation name > _syn.v

< variation name > _model.m

< variation name >_nativelink.tcl

< variation name > _tb.m

< variation name >_wave.do

Description

Generated synthesizable netlist. This file is required for Quartus II synthesis. It will be

added to your Quartus II project.

ModelSim TCL Script that runs the VHDL or Verilog HDL IP functional simulation model

and generated VHDL or Verilog testbench in the ModelSim simulation software.

A VHDL or Verilog HDL testbench file for the MegaCore function variation. The VHDL file

is generated when a VHDL top level has been chosen or the Verilog HDL file when a

Verilog HDL top level has been chosen.

Quartus II symbol file for the MegaCore function variation. You can use this file in the

Quartus II block diagram editor.

A VHDL component declaration file for the MegaCore function variation. Add the

contents of this file to any VHDL architecture that instantiates the MegaCore function.

A MegaCore function report file in hypertext markup language format.

A single Quartus II IP file is generated that contains all of the assignments and other

information required to process your MegaCore function variation in the Quartus II

compiler. You are prompted to add this file to the current Quartus II project when you

exit from the MegaWizard.

Quartus II vector File. This file provides simulation test vectors to be used for simulating

the customized NCO MegaCore function variation with the Quartus II software.

A VHDL or Verilog HDL file that defines a VHDL or Verilog HDL top-level description of

the custom MegaCore function variation. Instantiate the entity defined by this file inside

of your design. Include this file when compiling your design in the Quartus II software.

A VHDL or Verilog HDL output file that defines the IP functional simulation model.

Verilog HDL black-box file for the MegaCore function variation. Use this file when using

a third-party EDA tool to synthesize your design.

Memory initialization files in INTEL Hex format. These files are required both for

simulation with IP functional simulation models and synthesis using the Quartus II

software.

A timing and resource estimation netlist for use in some third-party synthesis tools.

MATLAB m-file describing a MATLAB bit-accurate model.

A Tcl script that can be used to assign NativeLink simulation testbench settings to the

Quartus II project.

MATLAB testbench file.

ModelSim Waveform file.

Notes to Table 2–1:

(1) < variation name > is a prefix variation name supplied automatically by IP Toolbench.

(2) The < entity name > prefix is added automatically. The VHDL code for each MegaCore instance is generated dynamically when you click Finish

so that the < entity name > is different for every instance. It is generated from the < variation name > by appending _st.

November 2013

Altera Corporation

NCO MegaCore Function

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